One way to conserve power in a system is to dynamically change the system clock rate when the system enters a low activity or low power state. Generally, the clock rate is changed to a fraction of the normal working frequency when entering a low power mode. The maximum power savings is achieved if the majority of the hardware subsystems of the system including any shared memory of the system can operate at the lowered clock rate. Conventionally, the clock rate of a system having a low power mode is changed asynchronously or the system includes additional hardware specifically configured for assisting in the clock rate change.